One or more exemplary embodiments relate to a scaler circuit, and more particularly to a scaler circuit which can generate images having different scaling ratios from a single image in a parallel manner, and devices having the same.
An image scaler may be a circuit which can scale-up (or up-scale) or scale-down (down-scale) an image or image data, or software which can perform an algorithm to up-scale or down-scale an image. For example, an image processing application (or application program) may resize a single image into a plurality of images for various purposes such as previews, recording, capture, and thumbnails.
When generating a plurality of resized images from the single input image using an image scaler which generates a single output image from the single input image, the image scaler needs to generate the plurality of resized images by reading the same image stored in a memory a plurality of times. In order to generate the plurality of resized images from the single input image within given time, a frequency of a clock signal supplied to the image scaler needs to be high. Accordingly, an image scaler which uses a clock signal having a high frequency causes an increase in the amount of power consumed by the image scaler and an image processing system having the same.